Solid state imagers are increasingly popular due to small size, low cost, and improved image quality. One such solid state imager is a CMOS imager. CMOS sensor technology enables a higher level of integration of an image array with associated processing circuits, which can be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and other imaging applications.
A CMOS imager circuit includes a focal plane array of pixel cells or “Pixels”, each Pixel including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel, as just described, perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) selection of a pixel for readout; and (5) output and amplification of a signal representing pixel charge. The charge at the storage region is typically converted to a pixel output voltage by the capacitance of the storage region and a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 generally illustrates a conventional CMOS pixel structure 50. As shown, a crystal silicon photodiode 49 is formed of two doped regions 10, 12 in a substrate 60. Circuitry, including transistors gates 18, 19, 27, 29 are formed for performing the pixel functions described briefly above. An active charge storage area 14 for storing photo-charges prior to signal readout is formed in a p-well region 61 between the two transistors 18, 19. Isolation regions 55 are also formed on either side of the pixel 50 for isolating the active regions of the pixel from adjacent pixels.
As pixel sizes continue to decrease, due to desirable scaling, conventional pixel structures, such as the pixel 50 shown in FIG. 1 have various shortcomings. Specifically, a smaller photodiode has lower quantum efficiency, higher cross talk, and reduced angular response, which make it difficult to continue shrinking the pixel size while maintaining a high sensor quality.
One suggested improvement to the conventional pixel structure 50 is illustrated in FIG.1A and is described in U.S. Patent Application Pub. No. US 2005-0269606 A1, assigned to Micron Technology, Inc., and incorporated herein by reference. As shown in FIG. 1A, an elevated photosensor 122 is formed above a surface 118 of a substrate 101 where the pixel circuitry is formed. The illustrated pixel circuitry includes transistors 106, 120, 127, and 129. The illustrated photosensor 122 comprises epitaxial layers 115, 116, 117 that are grown above the surface 118 of the substrate 101. The photosensor material of the elevated epitaxial layers 116, 117 is an amorphous silicon. The pixel 100 described in U.S. Patent Application Pub. No. US 2005-0269606 A1 has an increased fill factor over the pixel 50 illustrated in FIG. 1, as a greater portion of the top-down surface area of the pixel 100 is photosensitive.
The amorphous silicon used for the pixel in FIG. 1A, however, may not be desirable in all situations. For example, while amorphous silicon can be grown as an epitaxial layer, its inherent properties may not be as suitable for imaging purposes as those, for example, of crystal silicon. Accordingly, there is a need and desire for a pixel having a high fill factor and also having excellent photosenstive qualities. A simple and robust method of making the pixel is also desired.